Fault Detection Mechanism using Improved Watchdog Timer for Safety Application

Authors

  • B. B. Manjula Associate Professor, Department of Electronics and Communication Engineering, East West Institute of Technology, Bangalore, India
  • N. Santhosh Student, Department of Electronics and Communication Engineering, East West Institute of Technology, Bangalore, India
  • K. S. Ravikiran Student, Department of Electronics and Communication Engineering, East West Institute of Technology, Bangalore, India
  • K. Pooja Student, Department of Electronics and Communication Engineering, East West Institute of Technology, Bangalore, India
  • H. V. Sahana Student, Department of Electronics and Communication Engineering, East West Institute of Technology, Bangalore, India

Keywords:

FPGA, Verilog HDL, Xilinx ISE14.7

Abstract

This project describes the architecture and design of an improved configurable watchdog timer that can be employed in safety-critical applications. Watchdog timers are used in such systems to automatically handle and recover from operation time related failures. Several fault detection mechanisms are built into the watchdog, which adds to its robustness. This project also discusses the implementation of the proposed watchdog timer in a Field Programmable Gate Array (FPGA) Spartan3. The effectiveness of the proposed watchdog timer to detect and respond to faults. The language used is Verilog HDL and the simulation tool that used is Xilinx 14.7.

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Published

2021-07-20

How to Cite

[1]
B. B. Manjula, N. Santhosh, K. S. Ravikiran, K. Pooja, and H. V. Sahana, “Fault Detection Mechanism using Improved Watchdog Timer for Safety Application”, IJRESM, vol. 4, no. 7, pp. 204–207, Jul. 2021.

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Articles