Fault Detection Mechanism using Improved Watchdog Timer for Safety Application
Keywords:FPGA, Verilog HDL, Xilinx ISE14.7
This project describes the architecture and design of an improved configurable watchdog timer that can be employed in safety-critical applications. Watchdog timers are used in such systems to automatically handle and recover from operation time related failures. Several fault detection mechanisms are built into the watchdog, which adds to its robustness. This project also discusses the implementation of the proposed watchdog timer in a Field Programmable Gate Array (FPGA) Spartan3. The effectiveness of the proposed watchdog timer to detect and respond to faults. The language used is Verilog HDL and the simulation tool that used is Xilinx 14.7.
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Copyright (c) 2021 B. B. Manjula, N. Santhosh, K. S. Ravikiran, K. Pooja, H. V. Sahana
This work is licensed under a Creative Commons Attribution 4.0 International License.