AES-128 Algorithm Design with Verilog

Authors

  • Mahalsa Sai Dontha Department of Electronics and Communication Engineering, Sri Indu College of Engineering & Technology, Sheriguda, India

Keywords:

AES, cryptography, DES, encrypt, security

Abstract

The issue of multimedia data security has emerged as a matter of essential concern due to the increasing growth of digital data exchanges through unsecure networks. For this reason, multimedia files are encrypted using cryptographic protocols to prevent unauthorized access. The US government uses the symmetric block cipher Advanced Encryption Standard (AES) to protect sensitive information. The Advanced Encryption Standard (AES) is used to encrypt private information all over the world. This standard is built into both software and hardware. It is crucial for cybersecurity and the protection of digital information and government networks. Maintaining one's right to privacy is becoming more and more important, not just for regular citizens but also for governments that want to stop signal and data interception. Maintaining one's right to privacy is becoming more and more important, not just for regular citizens but also for governments that want to stop signal and data interception. With the rise of personal communications devices, people are asking for more privacy in conversations that used to be unprotected. The length of the key is the main determining factor between DES and AES. This is because they are both examples of symmetric key block ciphers (56 bit for DES). When encrypting messages that are bigger than the size of a block, the right mode of operation must be chosen. After AES has been implemented, I will explain how this mode of operation functions. The original Rijndael allowed for key and block sizes of any multiple of 32 bits, from a minimum of 128 bits up to a maximum of 256 bits. This was in contrast to AES, which supported blocks with a fixed-size support of 128 bits and a range of 128, 192, and 256-bit key sizes. However, AES has a limitation in that its maximum block size is 128 bits.

Downloads

Download data is not yet available.

Downloads

Published

15-08-2022

How to Cite

[1]
M. S. Dontha, “AES-128 Algorithm Design with Verilog”, IJRESM, vol. 5, no. 8, pp. 37–40, Aug. 2022.

Issue

Section

Articles