An Instinctive Error Encoder and Decoder Using XOR for Space Applications
Keywords:ECC (Error detection and correction Technique), Multiple cell upsets, XOR gates, Verilog HDL
Memory errors are a significant concern in advanced electronic circuits. As technology advances, on-chip memories become more susceptible to multiple bit errors. To address this issue, error detection and correction techniques (ECC) are used to identify and rectify corrupted data during transmission. In this study, a multiple bit error detection and correction method is proposed to reduce the impact of radiation-induced MCUs in memory for space applications. An inversion methodology is used to implement the encoding process, which involves analyzing diagonal bits, parity bits, and check bits through XOR operations. To recover data, an XOR operation is performed between the encoded bits and the recalculated encoded bits. This is followed by an analysis, verification, selection, and correction process. Compared to existing methods, this approach is more power-efficient and requires minimal space and delay. The proposed ECC scheme is designed to mitigate data corruption in volatile memories and is simulated and synthesized using Xilinx in Verilog HDL. This design approach provides high performance, low path delay, and improves synchronization.
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Copyright (c) 2023 Shanigaram Dilip, Varaganti Priyanka
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