Design and Implementation of Multiple-master, Multiple-slave Interface in AMBA AHB Protocol

Authors

  • S. Bhavana Surya Student, Department of Electronics and Communication Engineering, East West Institute of Technology, Bangalore, India
  • C. Hema Assistant Professor, Department of Electronics and Communication Engineering, East West Institute of Technology, Bangalore, India
  • M. Shruthi Priya Student, Department of Electronics and Communication Engineering, East West Institute of Technology, Bangalore, India
  • U. Devikarani Student, Department of Electronics and Communication Engineering, East West Institute of Technology, Bangalore, India
  • Ashwini S. Rathod Student, Department of Electronics and Communication Engineering, East West Institute of Technology, Bangalore, India

Keywords:

AHB, AMBA, SOC

Abstract

The development of VLSI technology makes it possible to combine millions of transistors on a single chip to form a SOC. The main disadvantage confronted here is to verify correct and loss-less communication between the IP cores within the SOC. This can be achieved using standard communication protocols like the Advanced Microcontroller Bus Architecture (AMBA). The Advanced High-Performance Bus (AHB) is an integral part of the AMBA protocol series. It is designed for high-performance system modules. In the proposed paper, the AMBA AHB system is designed and implemented using Verilog HDL. The design is simulated using Xilinx ISE 14.6.

Downloads

Download data is not yet available.

Downloads

Published

2021-07-15

How to Cite

[1]
S. B. Surya, C. Hema, M. S. Priya, U. Devikarani, and A. S. Rathod, “Design and Implementation of Multiple-master, Multiple-slave Interface in AMBA AHB Protocol”, IJRESM, vol. 4, no. 7, pp. 125–127, Jul. 2021.

Issue

Section

Articles